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| FUJITSU SEMICONDUCTOR DATA SHEET DS07-13510-2E 16-bit Proprietary Microcontroller CMOS F2MC-16F MB90F244 MB90F244 s DESCRIPTION The MB90F244 is a 16-bit microcontroller optimized for applications in mechatronics such as HDD units. The architecture of the MB90F244 is based on the MB90242A, and embedded with a 128-Kbyte flash memory. The instruction set is based on the AT architecture of the F2MC* family, with additional high-level language supporting instruction, expanded addressing modes, enhanced multiplication and division instructions, and improved bit processing instructions. In addition, long-word data can now be processed due to the inclusion of a 32-bit accumulator. The MB90F244 includes a variety of peripherals on chip, such as the device is equipped with 8-channel 8/10-bit A/D converter, UART, 3-channel 16-bit reload timers, 1-channel 16-bit timer, 4-channel 16-bit input capture and 4-channel DTP/external interrupts. Differences between the MB90F244 and MB90F243 to meet the 3.3 V 0.3 V power supply voltage are that the power consumption of the MB90F244 is about 10% less than that of the MB90F243 and the operating frequency of the MB90F244 is up to 50 MHz from 32 MHz of the MB90F243. * : F2MC stands for FUJITSU Flexible Microcontroller. s PACKAGE 80-pin Plastic TQFP (FPT-80P-M15) MB90F244 s FEATURES * Minimum execution time (target): 40.0 ns at 50 MHz oscillation (3.3 V 0.3 V) * Instruction set optimized for controller applications Variety of data types: bit, byte, word, long-word Expanded addressing modes: 25 types High coding efficiency Improvement of high-precision arithmetic operations through use of 32-bit accumulator Enhanced multiplication and division instructions (signed arithmetic operations) * Instruction set supports high-level language (C language) and multitasking Inclusion of system stack pointer Variety of pointers High instruction set symmetry Barrel shift instruction Stack check function * Improved execution speed: 8-byte queue * Powerful interrupt functions Interrupt processing time: 0.64 s at 50 MHz oscillation Priority levels: 8 levels (programmable) External interrupt inputs: 4 channels * Automatic transfer function independent of CPU Extended intelligent I/O service: Max.15 channels * 128-Kbyte flash memory Access time (min.) : 80 ns Sector structure of 16K + 512 x 2 + 7K + 8K + 32K + 64K Program/erase operations from both EPROM programmer and CPU through built-in flash memory interface circuit Built-in programming booster circuit for flash memory * Internal RAM: 1.152 kbyte According to mode settings, data stored on RAM can be executed as CPU instructions. * General-purpose ports: Max. 63 channels (single-chip mode) Max. 38 channels (external bus mode) * 18-bit timebase timer * Watchdog timer * UART: 8 bits x 1 channel * 8/16-bit I/O simple serial interface (max. 12.5 Mbps): 1 channel * 8/10-bit A/D converter: Analog inputs: 8 channels Resolution: 10 bits (switchable to 8 bits/10 bits) Conversion time: Min. 1 s Conversion result store register: 4 channels * 16-bit I/O timer 16-bit free-run timer: 1 channel (operating clock: 0.16 s) 16-bit input capture: 4 channels * 16-bit reload timer: 3 channels * Low-power consumption modes Sleep mode Stop mode Hardware standby mode * Packages: TQFP-80 (FPT-80P-M15) (For more information about the package, see section "s Package Dimensions.") (Continued) 2 MB90F244 (Continued) * PLL clock multiple function * CMOS technology * Power supply voltage: 3.3 V 0.3 V or 5.0 V 0.5 V (Varies with conditions such as the operating frequency. See section "s Electrical Characteristics.") 3 4 MB90F244 s PIN ASSIGNMENT VSS X0 X1 VCC 5 P00/D00/DQ0 P01/D01/DQ1 P02/D02/DQ2 P03/D03/DQ3 P04/D04/DQ4 P05/D05/DQ5 P06/D06/DQ6 P07/D07/DQ7 P10/D08/DQ8 P11/D09/DQ9 P12/D10/DQ10 P13/D11/DQ11 P14/D12/DQ12 P15/D13/DQ13 P16/D14/DQ14 P17/D15/DQ15 (Top view) (FPT-80P-M15) MD1 MD0 VCC P65/AN5 P67/AN7 P66/AN6 P63/AN3 P62/AN2 VSS P61/AN1 P60/AN0 AVSS AVRL AVRH AVCC P47/A23/ASR2/TIN2 P46/A22/ASR1/TIN1 P45/A21/ASR0/TIN0 P44/A20/SCK0 P43/A19/SOD0 P20/A00/AQ0 P21/A01/AQ1 P22/A02/AQ2 P23/A03/AQ3 P24/A04/AQ4 P25/A05/AQ5 P26/A06/AQ6 P27/A07/AQ7 VSS P30/A08/AQ8 P31/A09/AQ9 P32/A10/AQ10 P33/A11/AQ11 P34/A12/AQ12 P35/A13/AQ13 P36/A14/AQ14 P37/A15/AQ15 P40/A16/AQ16 P41/A17/AQ17 P42/A18/SID0/AQ18 RST P57/ASR3/INT3/BYTE P56/RD/CE P55/WRL/WR/OE P54/WRH/WE P53/HRQ P52/HAK P51/RDY CLK/RY/BY P82/INT2/ATG P81/INT1 P80/INT0 P75/SOD1 P74/SID1 P73/SCK1 P72/TOT2 P71/TOT1 P70/TOT0/AN4 HST MD2 MB90F244 s PIN DESCRIPTION Pin no. TQFP-80* 62 63 39 to 41 X0 X1 MD0 to MD2 C Operating mode selection input pins Connect directly to VCC5 or VSS. In the flash memory mode, these pins are set to be VID (= 12.0 V) input pins by performing a proper operation. External reset request input pin Hardware standby input pin General-purpose I/O port I/O pins for the lower 8 bits of the external data bus Data I/O pins for each operation command This function is valid in the flash memory mode. E General-purpose I/O port This function is valid when the external bus 8-bit mode. I/O pins for the upper 8 bits of the external data bus This function is valid when 16-bit bus mode. Data I/O pins for each operation command This function is valid in the flash memory mode. F General-purpose I/O port Output pins for the medium 8 bits of the external address bus Address input pins for each operation command This function is valid in the flash memory mode. F General-purpose I/O port This function is valid when the corresponding bit of the middle address control register specification is "port". Output pins for the medium 8 bits of the external address bus This function is valid when the corresponding bit of the middle address control register specification is "port". Address input pins for each operation command This function is valid in the flash memory mode. F General-purpose I/O port This function is valid when the corresponding bit of the upper address control register specification is "port". External address bus output pin of the bit 16 This function is valid when the corresponding bit of the upper address control register specification is "address". Address input pin for each operation command This function is valid in the flash memory mode. Pin name Circuit type A Function Crystal oscillator pins (50 MHz) 60 42 65 to 72 RST HST P00 to P07 D00 to D07 DQ0 to DQ7 B D E 73 to 80 P10 to P17 D08 to D15 DQ8 to DQ15 1 to 8 P20 to P27 A00 to A07 AQ0 to AQ7 10 to 17 P30 to P37 A08 to A15 AQ8 to AQ15 18 P40 A16 AQ16 *: FPT-80P-M15 (Continued) 5 MB90F244 Pin no. TQFP-80* 19 Pin name P41 Circuit type F Function General-purpose I/O port This function is valid when the upper address control register specification is "port". External address bus output pin of the bit 17 This function is valid when the corresponding bit of the upper address control register specification is "address". Address input pin for each operation command This function is valid in the flash memory mode. A17 AQ17 20 P42 F General-purpose I/O port This function is valid when the corresponding bit of the upper address control register specification is "port". External address bus output pin of the bit 18 This function is valid when the corresponding bit of the upper address control register specification is "address". UART #0 data input pin During UART #0 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. Address input pin for each operation command This function is valid in the flash memory mode. A18 SID0 AQ18 21 P43 G General-purpose I/O port This function is valid when the UART #0 data output is disabled and the corresponding bit of the upper address control register specification is "port". External address bus output pin of the bit 19 This function is valid when the UART #0 data output is disabled and the corresponding bit of the upper address control register specification is "address". UART #0 data output pin This function is valid when the UART #0 data output is enabled. A19 SOD0 22 P44 G General-purpose I/O port This function is valid when the UART #0 clock output is disabled and the corresponding bit of the upper address control register specification is "port". External address bus output pin of the bit 20 This function is valid when the UART #0 clock output is disabled and the corresponding bit of the upper address control register specification is "address". UART #0 clock I/O pin A20 SCK0 *: FPT-80P-M15 (Continued) 6 MB90F244 Pin no. TQFP-80* 23 Pin name P45 Circuit type G Function General-purpose I/O port This function is valid when the corresponding bit of the upper address control register specification is "port". External address bus output pin of the bit 21 This function is valid when the corresponding bit of the upper address control register specification is "address". 16-bit input capture #0 data input pin During 16-bit input capture #0 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. 16-bit timer #0 data input pin During 16-bit timer #0 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. A21 ASR0 TIN0 24 P46 G General-purpose I/O port This function is valid when the corresponding bit of the upper address control register specification is "port". External address bus output pin of the bit 22 This function is valid when the corresponding bit of the upper address control register specification is "address". 16-bit input capture #1 data input pin During 16-bit input capture #1 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. 16-bit timer #1 data input pin During 16-bit timer #1 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. A22 ASR1 TIN1 25 P47 G General-purpose I/O port This function is valid when the corresponding bit of the upper address control register specification is "port". External address bus output pin for the bit 23 This function is valid when the corresponding bit of the upper address control register specification is "address". 16-bit input capture #2 data input pin During 16-bit input capture #2 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. 16-bit timer #2 data input pin During 16-bit timer #2 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. A23 ASR2 TIN2 *: FPT-80P-M15 (Continued) 7 MB90F244 Pin no. TQFP-80* 53 Pin name P51 RDY Circuit type H Function General-purpose I/O port This function is valid when the ready function is disabled. Ready input pin This function is valid when the ready function is enabled. 54 P52 HAK H General-purpose I/O port This function is valid when the hold function is disabled. Hold acknowledge output pin This function is valid when the hold function is enabled. 55 P53 HRQ H General-purpose I/O port This function is valid when the hold function is disabled. Hold request input pin This function is valid and when the hold function is enabled. 56 P54 F General-purpose I/O port This function is valid in external bus 8-bit mode, or when WRH pin output is disabled. Write strobe output pin for the upper 8 bits of the data bus This function is valid in modes where the external bus 16-bit mode is enabled, and WRH pin output is enabled. Write enable input pin This function is valid in the flash memory mode. WRH WE 57 P55 WRL / WR OE 58 P56 RD CE 59 P57 ASR3 F F F General-purpose I/O port This function is valid when WRL pin output is disabled. Write strobe output pin for the lower 8 bits of the data bus This function is valid WRL pin output is enabled. Output enable input pin for each operation command This function is valid in the flash memory mode. General-purpose I/O port Read strobe output pin for the data bus Chip enable input pin for each operation command This function is valid in the flash memory mode. General-purpose I/O port 16-bit input capture #3 data input pin During 16-bit input capture #3 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. DTP/external interrupt #3 data input pin During DTP/external interrupt #3 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. Byte access control input pin This function is valid in the flash memory mode. INT3 BYTE *: FPT-80P-M15 (Continued) 8 MB90F244 Pin no. TQFP-80* 30, 31, 33, 34, 35, 36, 37 Pin name P60, P61, P62, P63, P66, P67, P65 AN0, AN1, AN2, AN3, AN6, AN7, AN5 Circuit type I Function N-ch open-drain type I/O ports When bits corresponding to the ADER are set to "0", reading instructions other than the read-modify-write group returns the pin level. The value written on the data register is output to this pin directly. 8/10-bit A/D converter analog input pins Use this function after setting bits corresponding to the ADER to "1" and setting corresponding bits of the data register to "1". 43 P70 J General-purpose I/O port This function is valid when the bit corresponded to ADER is set to "0" and also the output of 16-bit timer #0 is disabled. 16-bit timer output pin This function is valid when the bit corresponded to ADER is set to "0" and also the output of 16-bit timer #0 is enabled. 8/10-bit AD converter analog input pin This function can be used when the bit corresponded to ADER is set to "1" and also the bit correponded to the data resister is set to "1". TOT0 AN4 44, 45 P70, P72 TOT1, TOT2 G General-purpose I/O port This function is valid when the reload timer #1, and #2 output is disabled. 16-bit timer output pins This function is valid when the 16-bit timer #1, and #2 output is enabled. 46 P73 SCK1 G General-purpose I/O port This function is valid when the SSI #1 clock output is disabled. SSI #1 clock output I/O pin General-purpose I/O port This function is always valid. SSI #1 data input pin During SSI #1 input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. 47 P74 SID1 G 48 P75 SOD1 G General-purpose I/O port This function is valid when the SSI #1 data output is disabled. SSI #1 data output pin This function is valid when the SSI #1 data output is disabled. *: FPT-80P-M15 (Continued) 9 MB90F244 (Continued) Pin no. TQFP-80* 49, 50 Pin name P80, P81 INT0, INT1 Circuit type G Function General-purpose I/O port This function is always valid. DTP/external interrupt input pin When external interrupts are enabled, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. G General-purpose I/O port This function is always valid. DTP/external interrupt input pin When external interrupts are enabled, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using them for output deliberately. Because an input to this pin is clamped to Low when the CPU stops, use INT0 or INT1 to wake up the system from the stop mode. 8/10-bit A/D converter trigger input pin When 8/10-bit A/D converter is waiting for activation, this input may be used at any time; therefore, it is necessary to stop output by other functions on this pin, except when using it for output deliberately. G CLK output pin Open-drain pin output ready/busy signal in the program deleting operation This function is valid in the flash memory mode. Power supply Power supply Power supply Power supply Power supply Power supply Power supply Digital circuit power supply pin Power supply voltage (5.0 V) input pin for flash memory Digital circuit power supply (GND) pin 51 P82 INT2 ATG 52 CLK RY/BY 38 64 9, 32, 61 26 VCC VCC5 VSS AVCC Analog circuit power supply pin This power supply must only be turned on or off when electric potential of AVCC or greater is applied to VCC. 8/10-bit A/D converter external reference voltage input pin This pin must only be turned on or off when electric potential of AVRH or greater is applied to AVCC. 8/10-bit A/D converter external reference voltage input pin Analog circuit power supply (GND) pin 27 AVRH 28 29 *: FPT-80P-M15 AVRL AVSS 10 MB90F244 s I/O CIRCUIT TYPE Type A Clock halt Circuit Remarks * 50 MHz * Oscillation feedback resistor: Approximately 1 M X0 X1 R Clock input B * CMOS-level hysteresis input (without standby control) * Pull-up resistor: Approximately 50 k R P-ch Tr N-ch Tr Diffusion resistor Digital input CMOS C * CMOS-level input * High voltage control for flash memory testing Control signal Mode input Diffusion resistor D * CMOS-level hysteresis input (without standby control) P-ch Tr Diffusion resistor N-ch Tr Digital input CMOS (Continued) 11 MB90F244 (Continued) Type E Digital output Digital output Flash memory input Digital input TTL Circuit Remarks * CMOS-level output * TTL-level input (with standby control) Diffusion resistor Flash memory mode Standby control signal TTL F Digital output Digital output Flash memory input Digital input CMOS * CMOS-level output * CMOS-level hysteresis input * TTL-level input (flash memory mode) (with standby control) Diffusion resistor Flash memory mode Standby control signal TTL G Digital output Diffusion resistor Digital output * CMOS-level output * CMOS-level hysteresis input (with standby control) Standby control signal Digital input CMOS H Digital output Diffused resistor Digital output * CMOS-level output * TTL-level input (with standby control) Standby control signal Digital input TTL (Continued) 12 MB90F244 (Continued) Type I Circuit Remarks * N-ch open-drain CMOS-level output * CMOS-level hysteresis input (analog input) (with analog input control) Digital output Diffusion resistor Analog input Analog input control Digital input CMOS J Digital output Digital output Diffusion resistor * N-ch open-drain CMOS-level output * CMOS-level hysteresis input (analog input) (with analog input control) Analog input Digital input CMOS Analog input control 13 MB90F244 s HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to the input or output pins other than medium-and high-voltage pins or if higher than the voltage which shown on "1. Absolute Maximum Ratings" in section "s Electrical Characteristics"is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. In addition, for the same reasons take care to prevent the analog power supply from exceeding the digital power supply. 2. Treatment of Unused Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistors. 3. Precautions when Using an External Clock When an external clock is used, drive X0 only. * For example an external clock X0 X1 4. Power Supply Pins When there are several VCC and VSS pins, those pins that should have the same electric potential are connected within the device when the device is designed in order to prevent misoperation, such as latch-up. However, all of those pins must be connected to the power supply and ground externally in order to reduce unnecessary emissions, prevent misoperation of strobe signals due to an increase in the ground level, and to observe the total output current standards. In addition, give a due consideration to the connection in that current supply be connected to VCC and VSS with the lowest possible impedance. Finally, it is recommended to connect a capacitor of about 0.1 F between VCC and VSS near this device as a bypass capacitor. 14 MB90F244 5. Crystal Oscillation Circuit Noise in the vicinity of the X0 and X1 pins will cause this device to operate incorrectly. Design the printed circuit board so that the bypass capacitor connecting X0 and X1 pins and the crystal oscillator (or ceramic oscillator) to ground is located as close to the device as possible. In addition, because printed circuit board artwork in which the area around the X0 and X1 pins is surrounded by ground provides stable operation, such an arrangement is strongly recommended. 6. Sequence for Applying the A/D Converter Power Supply and the Analog Inputs Always be sure to apply the digital power supply (VCC) before applying the A/D converter power supply (AVCC, AVRH, and AVRL) and the analog inputs (AN0 to AN7). In addition, when the power is turned off, turn off the A/D converter power supply and the analog inputs first, and then turn off the digital power supply. (Turning on or off the analog and digital power supplies simultaneously will not cause any problems.) Whether applying or cutting off the power, be certain that AVRH does not exceed AVCC. 7. External Reset Input To reliably reset the controller by inputting an "L" level to the RST pin, ensure that the "L" level is applied for at least five machine cycles. 8. HST Pin When turning on the system, be sure to set the HST pin to "H" level. Never set the HST pin to "L" level while the RST pin is in "L" level. 9. CLK Pin X1 ex. 50 MHz STOP To internal blocks X0 Divide by 2 circuit CLK STOP Note: CLK pin cannot use as I/O port. Care must be taken that this is different from standard specification for F2MC-16F family. 15 MB90F244 10.Specifed Interrupt Sequence When the interrupt stack area is allocated to the external memory, even if the higher priority level interrupt may generate while the former interrupt is waiting in the stack area, the latter higher priority level interrupt routine has to wait untill the former interrupt routine is excuted. In this case the former interrupt routine is excuted in the latter higher priority level. Normal interrupt sequence Interrupt level (ILM = 0) Interrupt level (ILM = 1) Interrupt level (ILM = 7) B Specified interrupt sequence C B C A B interrupt generation A A B interrupt generation A C interrupt generation A: Main routine operation (ILM = 7) B: Priority 0 interrupt routine (ILM = 0) C: Priority 1 interrupt routine (ILM = 1) C interrupt generation Program operation Program transition (Resister stack) 16 MB90F244 s BLOCK DIAGRAM SCK0 SID0 SOD0 UART 16-bit timer ASR0 to ASR3 SCK1 SID1 SOD1 AVCC AVRH AVRL AVSS AN0 to AN7 ATG 8/16-bit I/O simple serial interface 16-bit input capture (ICU) x 4 channels 8/10-bit A/D converter I/O port x 63 External bus interface TIN0/TOT0 to TIN2/TOT2 16-bit reload timer F2MC-16F CPU P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P51 to P57 P60 to P63 P65 to P67 P70 to P75 P80 to P82 D00 to D15 A00 to A23 CLK RDY HAK HRQ WRH WRL/WR RD DQ0 to DQ15 AQ0 to AQ18 WE OE CE BYTE RY/BY Internal data bus RAM INT0 to INT3 DTP/external Interrupt x 4 channels Flash memory interface X0 X1 RST HST MD0 to MD2 Flash memory Clock controller VCC 5 PLL Other pins VCC, VSS 17 MB90F244 s F2MC-16L CPU PROGRAMMING MODEL * Dedicated registers AH AL USP SSP PS PC USPCU SSPCU USPCL SSPCL DPR PCB DTB USB SSB ADB 8 bits 16 bits 32 bits Accumulator User stack pointer System stack pointer Processor status Program counter User stack upper limit register System stack upper limit register User stack lower limit register System stack lower limit register Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register * General-purpose registers Max. 32 banks R7 R5 R3 R1 RW3 R6 R4 R2 R0 RL2 RL3 RL1 RW2 RW1 000180H + (RP x 10 H ) RW0 16 bits RL0 * Processor status (PS) ILM RP -- I S T N CCR Z V C 18 MB90F244 s MEMORY MAP Single-chip mode FFFFFF H Flash memory ROM FE0 0 0 0 H Internal ROM/ external bus mode External ROM/ external bus mode Flash memory ROM : access inhibited 0 0 0 5 7F H RAM RAM RAM : Internal access memory 000100H 0 0 0 0C0 H 000020H 000000H Peripheral Peripheral Peripheral : Exernal access memory I/O I/O I/O 19 MB90F244 s I/O MAP Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H to 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H to 00001FH 000020H 000021H 000022H 000023H 000024H to 000027H 000028H 000029H 00002AH 00002BH 00002CH to 00002EH UMC0 USR0 UIDR0/ UODR0 URD0 Mode control register 0 Status register 0 Input data register 0/ output data register 0 Rate and data register 0 (Vacancy) SCR1 SSR1 SDR1L SDR1H Serial control status register 1 Serial status register 1 Serial data register 1 (L) Serial data register 1 (H) (Vacancy) R/W R/W R/W R/W UART ch. 0 00000100 B 00010000 B XXXXXXXX B 00000000 B DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 ADER DDR7 DDR8 Port 0 data direction register Port 1 data direction register Port 2 data direction register Port 3 data direction register Port 4 data direction register Port 5 data direction register Analog input enable register Port 7 data direction register Port 8 data direction register (Vacancy) R/W R/W R/W R/W 8/16-bit I/O simple serial interface ch. 1 10000000 B - - - - - - 00 B XXXXXXXX B XXXXXXXX B Register name PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register (Vacancy) R/W R/W R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Analog input enabled Port 7 Port 8 00000000 B 00000000 B 00000000 B 00000000 B 00000000 B 0000000- B 11111111B --000000 B - - - - - 00 0 B Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Initial value XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXX- B 111-1111 B - - XXXXXX B - - - - - XXXB (Continued) 20 MB90F244 Address 00002FH 000030H 000031H 000032H 000033H to 00003FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H to 00005FH 000060H 000061H 000062H 000063H 000064H 000065H Register name CKSCR ENIR EIRR ELVR Register Clock selection register DTP/interrupt enable register DTP/interrupt source register Request level setting register (Vacancy) Read/ write R/W R/W R/W R/W Resource name PLL DTP/external interrupt Initial value - - - - 1 1 0 0B ----0000B ----0000B 00000000B TMCSR0 TMR0 TMRLR0 Timer control status register #0 16-bit timer register #0 16-bit reload register #0 (Vacancy) R/W R/W R R W W 16-bit timer #0 0 0 0 0 0 0 0 0B - - - - 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB TMCSR1 TMR1 TMRLR1 Timer control status register #1 16-bit timer register #1 16-bit reload register #1 (Vacancy) R/W R/W R R W W 16-bit timer #1 0 0 0 0 0 0 0 0B - - - - 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB TMCSR2 TMR2 TMRLR2 Timer control status register #2 16-bit timer register #2 16-bit reload register #2 R/W R/W R R W W 16-bit timer #2 0 0 0 0 0 0 0 0B - - - - 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Vacancy) R R R R R/W (Vacancy) XXXXXXXXB XXXXXXXXB 16-bit input XXXXXXXXB capture 0 and 1 XXXXXXXXB 00000000B ICP0 ICP1 ICS0 Input capture register 0 Input capture register 1 Input capture control status register 0 and 1 (Continued) 21 MB90F244 Address 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH 00006DH 00006EH 00006FH 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH to 00008FH 000090H to 00009EH 00009FH Register name ICP2 ICP3 ICS1 Register Input capture register 2 Input capture register 3 Input capture control status register 2 and 3 (Vacancy) Read/ write R R R/W Resource name Initial value XXXXXXXXB XXXXXXXXB 16-bit input XXXXXXXXB capture 2 and 3 XXXXXXXXB 00000000B TCDT TCCS ADCS 1 ADCS 2 ADCT 1 ADCT 2 ADTL0 ADTH0 ADTL1 ADTH1 ADTL2 ADTH2 ADTL3 ADTH3 Timer data register Timer control status register (Vacancy) A/D control status register 1 A/D control status register 2 Conversion time setting register 1 Conversion time setting register 2 A/D data register 0 (L) A/D data register 0 (H) A/D data register 1 (L) A/D data register 1 (H) A/D data register 2 (L) A/D data register 2 (H) A/D data register 3 (L) A/D data register 3 (H) (Vacancy) R R R/W R/W R/W R/W R/W R R R R R R R R 8/10-bit A/D converter 16-bit freerun timer 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 00000000B 0 0 0- 0 0 0 0B - 0 0 0- - 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB - - - - - - XXB XXXXXXXXB - - - - - - XXB XXXXXXXXB - - - - - - XXB XXXXXXXXB - - - - - - XXB (System reserved area)*1 Delayed interrupt source generation/ release register Standby control register Middle address control register High address control register External pin control register Delayed interrupt generation - - - - - - - 0B module Low-power consumption mode 0 0 0 1XXXXB *2 External pin *2 *2 DIRR R/W 0000A0H 0000A3H 0000A4H 0000A5H STBYC MACR HACR EPCR R/W W W W (Continued) 22 MB90F244 (Continued) Address 0000A8H 0000A9H 0000AEH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H to 0000FFH Explanation of read/write R/W : Readable and writable R : Read only W : Write only Explanation of initial values 0 : The initial value of this bit is "0". 1 : The initial value of this bit is "1". X: The initial value of this bit is undefined. - : This bit is unused. No initial value is defined. *1: Access prohibited. *2: The initial values are changed depending on a bus mode. *3: The only area available for the external access below address 0000FFH is this area. Addresses not explained in the table are "(reserved area)"; accesses to these areas are handled accesses to internal areas. No access signal is generated for the external bus. Note: Do not use any "(vacancy)". Register name WTC TBTC FMCS ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Register Watchdog timer control register Timebase timer control register Control status register Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 (External area)*3 Read/ write R/W R/W R/W R/W*3 R/W*3 R/W* R/W* 3 3 Resource name Watchdog timer Timebase timer Flash memory Initial value XXXXXXXXB 0XX0 0 0 0 0 B 0 0 0 X0- - 0B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B R/W*3 R/W*3 R/W*3 R/W* R/W* 3 3 Interrupt controller R/W*3 R/W*3 R/W* R/W* R/W* 3 3 3 R/W*3 R/W*3 23 MB90F244 s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol VCC VCC5 Power supply voltage AVCC AVRH AVRL Input voltage Output voltage "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total average output current Power consumption Operating temperature Storage temperature *1: *2: *3: *4: VI1 VI2 VO IOL IOLAV IOL IOLAV IOH IOHAV IOHAV PD TA Tstg Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 0 -55 Max. VSS + 4.0 VSS + 7.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VCC + 0.3 VCC5 + 0.3 VCC + 0.3 10 3 60 30 -10 -3 -60 -30 350 +70 +125 Unit V V V V V V V V mA mA mA mA mA mA mA mA mW C C *1 *2 *2 *2 *3 *4 *3 Remarks "H" level total maximum output current IOH VCC5 must always exceed VCC. AVCC, AVRH and AVRL must not exceed VCC. Also AVRL must not exceed AVRH. VI1 and VO must not exceed VCC + 0.3 V. VI2 must not exceed VCC5 + 0.3 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 24 MB90F244 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter VCC Power supply voltage VCC VCC5 Operating temperature TA Symbol Value Min. 3.0 3.0 4.5 0 Max. 3.6 3.6 5.5 +70 Unit V V V C Remarks Normal operation Maintaining the stop status WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 25 MB90F244 3. DC Characteristics (VCC5 = 5.0 V 0.5 V, VCC = 3.3 V 0.3 V, AVSS = VSS = 0.0 V, TA = 0C to +70C) Parameter Symbol VIH2 VIH1S "H" level input voltage VIH2S VIH2S5 VIHM VIL2 VIL1S "L" level input voltage VIL2S VIL2S5 VILM "H" level output voltage "L" level output voltage VOH VOL IIH1 Pin name -- P60 to P63, P65 to P67, P70 -- RST, HST MD0 to MD2 -- P60 to P63, P65 to P67, P70 -- RST, HST MD0 to MD2 All ports VCC = 3.0 V except port 6 IOH = -1.6 mA All ports VCC = 3.0 V IOL = 2.0 mA -- Condition Value Min. 0.7 VCC 0.8 VCC 0.8 VCC Max. VCC5 + 0.3 VCC + 0.3 VCC5 + 0.3 Unit V V V V V V V V V V V V A CMOS input A TTL input A CMOS hysteresis input A CMOS hysteresis input Only port 6 Remarks TTL input CMOS hysteresis input CMOS hysteresis input CMOS hysteresis input CMOS input TTL input CMOS hysteresis input CMOS hysteresis input CMOS hysteresis input CMOS input 0.8 VCC5 VCC5 + 0.3 0.7 VCC5 VCC5 + 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VCC - 0.3 -- -- 0.2 VCC 0.2 VCC 0.2 VCC 0.2 VCC5 0.2 VCC5 -- 0.4 -10 VCC = 3.6 V MD0 to MD2 VCC5 = 5.5 V VIH = 0.7 VCC5 -- VCC = 3.6 V VCC5 = 5.5 V VIH = 2.2 V IIH2 "H" level input current IIH3 -- -10 VCC = 3.6 V Except port 6, VCC5 = 5.5 V RST, HST VIH = 0.8 VCC P60 to P63, P65 to P67 VCC = 3.6 V VCC5 = 5.5 V VIH = 0.7 VCC -- -10 IIH4 -- -10 IIL1 VCC = 3.6 V MD0 to MD2 VCC5 = 5.5 V VIL = 0.3 VCC5 -- VCC = 3.6 V VCC5 = 5.5 V VIL = 0.8 V -- 10 A CMOS input A TTL input A CMOS hysteresis input A CMOS hysteresis input Only port 6 IIL2 "L" level input current IIL3 -- 10 VCC = 3.6 V Except port 6, VCC5 = 5.5 V RST, HST VIL = 0.2 VCC P60 to P63, P65 to P67 VCC = 3.6 V VCC5 = 5.5 V VIL = 0.3 VCC -- 10 IIL4 -- 10 (Continued) 26 MB90F244 (Continued) (VCC5 = 5.0 V 0.5 V, VCC = 3.3 V 0.3 V, AVSS = VSS = 0.0 V, TA = 0C to +70C) Parameter Symbol Pin name ICC1 ICC1 ICC51 ICC2 Power supply current*1 VCC VCC VCC5 VCC CPU normal mode at 25 MHz CPU normal mode at 25 MHz Condition VCC = 3.15 V to 3.6 V VCC = 3.3 V 0.15 V -- VCC = 3.15 V to 3.6 V VCC = 3.3 V 0.15 V -- CPU sleep mode At 25 MHz CPU stop mode TA = +25C -- VCC = 3.3 V VCC5 = 5.0 V -- -- Value Min. Typ. Max. -- -- -- -- -- -- -- -- 50 45 33 50 Unit mA mA mA Remarks Flash memory read state Flash memory read state Flash memory read state Flash memory mA program/erase state Flash memory mA program/erase state Flash memory mA program/erase state mA mA A A pF k A V ICC2 VCC -- -- 45 ICC52 ICCS ICC5S ICCH ICC5H Input capacitance Pull-up resistor Open-drain output leakage voltage Low VCC5 lock voltage*2 CIN RPULL ILEAK VLKO VCC5 VCC VCC5 VCC VCC5 Except VCC, VCC5, VSS RST Port 6 -- -- -- -- -- -- -- 22 -- TBD -- -- -- -- -- 10 -- -- -- 53 20 5 100 100 -- 220 10 3.6 *1: Because the current values are tentative values, they are subject to change without notice due to our efforts to improve the characteristics of these devices. *2: To prevent improper commands from being activated during rise and fall of VCC5, the internal VCC5 detection circuit of the flash memory allows only read accesses and ignores write accesses while VCC5 is lower than VLKO. 27 MB90F244 4. Flash Memory Programming/Eraseing Characteristics (VCC5 = 5.0 V 0.5 V, VCC = 3.3 V 0.3 V, AVSS = VSS = 0.0 V, TA = 0C to +70C) Parameter Sector eraseing time Chip eraseing time Byte programmimg time Chip programming time Erase/program cycle TA = +25C, VCC = 3.3 V, VCC5 = 5.0 V Condition Min. -- -- -- -- -- 100 Value Typ. 1.5 -- 16 2.1 -- Max. 13.5 27.0 -- -- -- Unit sec sec s sec cycles Remarks Except for the write time before internal erase operation Except for the write time before internal erase operation Except for the over head time of the system Except for the over head time of the system * : The internal automatic algorithm continues operations for up to 48 ms, for each 1-byte writing operation. 28 MB90F244 5. AC Characteristics (1) Clock Timing (VCC = 3.3 V 0.3 V, VCC5 = 5.0 V 0.5 V, AVSS = VSS = 0.0 V, TA = 0C to +70C) Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time * Clock timing tC Symbol FC FC tC PWH, PWL tCR, tCF Pin name X0, X1 X0, X1 X0, X1 X0 X0 Condition VCC = 3.15 V to 3.6 V VCC = 3.3 V 0.3 V Value Min. -- -- 1/FC Max. 50 40 -- -- 8 Unit MHz MHz ns ns ns Remarks -- 10 -- 0.7 VCC 0.3 VCC PWH tCF PWL tCR * Relationship between clock frequency and power supply voltage 3.6 Power supply voltagse VCC (V) Operation assurunce range (TA = -0C to +70C) 3.15 3.0 40 Source oscillation clock FC (MHz) 50 29 MB90F244 (2) Clock Output Timing (VCC = 3.3 V 0.3 V, VCC5 = 5.0 V 0.5 V, AVSS = VSS = 0.0 V, TA = 0C to +70C) Parameter Cycle time CLK CLK Symbol tCYC tCHCL Pin name CLK CLK Condition -- Value Min. 2 tC* Max. -- Unit ns ns Remarks 1 tCYC/2 - 15 1 tCYC/2 + 15 * : For information on tC (clock cycle time), see "(1) Clock Timing." tCYC tCHCL 2.0 V CLK 0.8 V 2.0 V (3) Reset and Hardware Standby Input (VCC = 3.3 V 0.3 V, VCC5 = 5.0 V 0.5 V, AVSS = VSS = 0.0 V, TA = 0C to +70C) Parameter Reset input time Symbol tRSTL Pin name RST HST Condition -- Value Min. 5 tCYC* 5 tCYC* Max. -- -- Unit ns ns Remarks Hardware standby input time tHSTL * : For information on tCYC (cycle time), see "(2) Clock Output Timing." Note: When hardware standby input is given, the machine cycle is simultaneously selected to be divide-by-32. tRSTL, tHSTL RST HST 0.2 VCC5 0.2 VCC5 30 MB90F244 (4) Power-on Reset (AVSS = VSS = 0.0 V, TA = 0C to +70C) Parameter Power supply rising time Power supply cut-off time Symbol tR tOFF Pin name VCC, VCC5 VCC, VCC5 Condition -- Value Min. -- 1 Max. 30 -- Unit ms ms * Remarks * : Before the power supply rising, VCC must be lower than 0.2 V. Note: The above standards are the values needed in order to activate a power-on reset. tR 2.1 V VCC 0.2 V 0.2 V tOFF 0.2 V If power supply voltage needs to be changed in the course of operation, a smooth voltage rise is recommended by suppressing the voltage variation as shown below. 3.3 V VCC 3.0 V Hold RAM data VSS It is recommended that the rate of increase in the voltage be kept to no more than 50 mV/ms. 31 MB90F244 (5) Bus Read Timing (VCC = 3.3 V 0.3 V, VCC5 = 5.0 V 0.5 V, AVSS = VSS = 0.0 V, TA = 0C to +70C) Parameter Address cycle time RD pulse width RD data read time Valid address data read time RD data hold time RD address valid time Symbol tACYC tRLRH tRLDV tAVDV tRHDX tRHAX Pin name AN23 to AN00 AN23 to AN00 RD D15 to D00 D15 to D00 D15 to D00 AN23 to AN00 AN23 to AN00, CLK RD, CLK -- Condition Value Min. 2 tCYC* - 10 1 tCYC*/2 - 13 1 tCYC* - 20 -- -- 0 1 tCYC*/2 - 20 1 tCYC*/2 - 20 1 tCYC*/2 - 20 Max. -- -- -- 1 tCYC* - 30 3 tCYC*/2 - 30 -- -- -- -- Unit Remarks ns ns ns ns ns ns ns ns ns Valid address RD time tAVRL Valid address CLK time tAVCH RD CLK time tRLCL * : For information on tCYC (cycle time), see "(2) Clock Output Timing." tAVCH tRLCL 2.0 V CLK tAVRL 0.8 V tRLRH RD 0.8 V tACYC 2.0 V tRHAX AN23 to AN00 2.0 V 0.8 V 2.0 V 0.8 V tRLDV tAVDV tRHDX 2.0 V 0.8 V D 15 to D00 2.0 V 0.8 V 32 MB90F244 (6) Bus Write Timing (VCC = 3.3 V 0.3 V, VCC5 = 5.0 V 0.5 V, AVSS = VSS = 0.0 V, TA = 0C to +70C) Parameter Symbol Pin name AN23 to AN00 WRL, WRH D15 to D00 D15 to D00 AN23 to AN00 WRL, WRH, CLK -- Condition Value Min. 1 tCYC*/2 - 13 1 tCYC* - 20 1 tCYC* - 33 1 tCYC*/2 - 15 1 tCYC*/2 - 15 1 tCYC*/2 - 20 Max. -- -- -- -- -- -- Unit Remarks ns ns ns ns ns ns Valid address WR time tAVWL WR pulse width Write data WR time WR Data hold time tWLWH tDVWH tWHDX WR Address valid time tWHAX WR CLK time tWLCL * : For information on tCYC (cycle time), see "(2) Clock Output Timing." tWLCL CLK WR (WRL, WRH) tAVWL tWLWH 0.8 V 2.0 V 0.8 V tWHAX AN23 to AN00 2.0 V 0.8 V tDVWH 2.0 V 0.8 V tWHDX D 15 to D00 0.7 V Write data 0.2 V 0.7 V 0.2 V 33 MB90F244 (7) Ready Input Timing (VCC = 3.3 V 0.3 V, VCC5 = 5.0 V 0.5 V, AVSS = VSS = 0.0 V, TA = 0C to +70C) Parameter RDY setup time RDY hold time Symbol Pin name tRYHS tRYHH RDY RDY Condition Source oscillation 50 MHz Value Min. 15 0 Max. 38 38 Unit ns ns Remarks Note: If the RDY setup time is insufficient, use the auto ready function. CLK 2.0 V 0.8 V tRYHH 2.0 V RD/WR tRYHS RDY AN23 to AN00 0.8 VCC 0.8 VCC External address D15 to D00 D15 to D00 Wait cycle Read data Wait cycle Write data (8) Hold Timing (VCC = 3.0 V 0.3 V, VCC5 = 5.0 V 0.5 V, AVSS = VSS = 0.0 V, TA = 0C to +70C) Parameter Pin floating HAK time Symbol Pin name tXHAL HAK HAK Condition -- Value Min. 30 1 tCYC* Max. 1 tCYC* 2 tCYC* Unit ns ns Remarks HAK time Pin valid time tHAHV * : For information on tCYC (cycle time), see "(2) Clock Output Timing." Note: At least one cycle is required from the time when HRQ is fetched until HAK changes. HRQ HAK tXHAL 0.2 V 0.8 V tHAHV Pins 2.0 V 0.8 V 2.0 V 0.8 V 34 MB90F244 (9) UART Timing (VCC = 3.3 V 0.3 V, VCC5 = 5.0 V 0.5 V, AVSS = VSS = 0.0 V, TA = 0C to +70C) Parameter Symbol Pin name -- -- -- -- -- -- -- -- -- For external shift clock mode output pin, CL = 80 pF For internal shift clock mode output pin, CL = 80 pF Condition Value Min. 8 tCYC* -80 100 60 4 tCYC* 4 tCYC* -- 60 60 Max. -- 80 -- -- -- -- 150 -- -- Unit ns ns ns ns ns ns ns ns ns Remarks Serial clock cycle time tSCYC SCK SOD delay time Valid SID SCK SCK Valid SID hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOD delay time delay time Valid SID SCK SCK Valid SID hold time tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX * : For information on tCYC (cycle time), see "(2) Clock Output Timing." Notes: * These are the AC characteristics for CLK synchronous mode. * CL is the load capacitance added to pins during testing. 35 MB90F244 * Internal shift clock mode tSCYC SCK0 0.8 V tSLOV 2.0 V 0.8 V SOD0 2.0 V 0.8 V tIVSH tSHIX 0.8 VCC 2.0 VCC SID0 0.8 VCC 2.0 VCC * External shift clock mode tSLSH tSHSL SCK0 0.8 VCC tSLOV 2.0 VCC 0.8 VCC 2.0 VCC SOD0 2.0 VCC 0.8 VCC tIVSH tSHIX 0.8 VCC 2.0 VCC SID0 0.8 VCC 2.0 VCC 36 MB90F244 (10) Serial I/O Timing (VCC = 3.3 V 0.3 V, VCC5 = 5.0 V 0.5 V, AVSS = VSS = 0.0 V, TA = 0C to +70C) Parameter Symbol Pin name -- -- -- -- For internal shift clock mode output pin, CL = 80 pF Condition Value Min. 2 tCYC* -- -15 1/2 tCYC* Max. -- 1 tCYC*/2 -- -- Unit Remarks ns ns ns ns Serial clock cycle time tSCYC SCK SOD delay time Valid SID SCK SCK Valid SID hold time tSLOV tIVSH tSHIX * : For information on tCYC (cycle time), see "(2) Clock Output Timing." Note: CL is the load capacitance added to pins during testing. * Internal shift clock mode tSCYC SCK1 0.8 V tSLOV 2.0 V 0.8 V SOD1 2.0 VCC 0.8 VCC tIVSH tSHIX 0.8 VCC 2.0 VCC SID1 0.8 VCC 2.0 VCC 37 MB90F244 (11) Timer Input Timing (VCC = 3.0 V 0.3 V, VCC5 = 5.0 V 0.5 V, AVSS = VSS = 0.0 V, TA = 0C to +70C) Parameter Input pulse width Symbol tTIWH, tTIWL Pin name ASR0 to ASR3, TIN0 to TIN2 Condition -- Value Min. 4 tCYC* Max. -- Unit ns Remarks * : For information on tCYC (cycle time), see "(2) Clock Output Timing." ASR0 to ASR3 TIN0 to TIN2 2.0 V 2.0 V 0.8 V tTIWH tTIWL 0.8 V (12) Timer Output Timing (VCC = 3.0 V 0.3 V, VCC5 = 5.0 V 0.5 V, AVSS = VSS = 0.0 V, TA = 0C to +70C) Parameter CLK Change time Symbol tTO Pin name TOT0 to TOT2 Condition VCC = 3.3 V 0.3 V Value Min. -- Max. 40 Unit Remarks ns CLK 2.0 V 2.0 V TOT0 to TOT2 0.8 V tTO 38 MB90F244 (13) Trigger Input Timing (VCC = 3.0 V 0.3 V, VCC5 = 5.0 V 0.5 V, AVSS = VSS = 0.0 V, TA = 0C to +70C) Parameter Input pulse width Symbol tTRGH, tTRGL Pin name ATG, INT0 to INT3 Condition -- Value Min. 5 tCYC* Max. -- Unit ns Remarks * : For information on tCYC (cycle time), see "(2) Clock Output Timing." ATG INT0 to INT3 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tTRGL tTRGH 39 MB90F244 6. A/D Converter Electrical Characteristics (VCC = 3.3 V 0.3 V, VCC5 = 5.0 V 0.5 V, AVSS = VSS = 0.0 V, TA = 0C to +70C) Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Symbol Pin name -- -- -- -- -- V0T V0T VFST VFST -- -- -- -- -- AN0 to AN3, AN5 to AN7 AN4 -- -- -- AN0 to AN3, AN5 to AN7 AN4 AN0 to AN3, AN5 to AN7 AN4 -- -- -- -- -- AN0 to AN7 -- Condition Min. -- -- -- -- -- AVRL -1.0 LSB AVRL -1.0 LSB AVRH -4.0 LSB AVRH -2.0 LSB Value Typ. 8, 10 8 -- -- -- AVRL +1.0 LSB AVRL +1.0 LSB AVRH -1.0 LSB AVRH -1.0 LSB Max. 10 8 T.B.D T.B.D T.B.D AVRL +4.0 LSB AVRL +1.5 LSB AVRH +1.0 LSB AVRH +1.0 LSB Unit bit Remarks bit LSB Target: 4.0 LSB Target: 2.0 LSB Target: 1.9 mV mV mV mV s ns ns ns ns A V V V mA mA A mA A No rating for AN4 because LSB of calculated by 8-bit precision 8-bit precision in calculation 8-bit precision in calculation Full-scale transition voltage Conversion time Sampling period Conversion period a Conversion period b Conversion period c Setup by ADCT register VCC = 3.3 V 0.3 V*1 1.00 440 120 120 200 -- -- -- -- -- -- 0.1 -- -- -- 7 7 -- 1.0 -- -- -- -- -- -- -- 3 AVRH AVCC AVRH - 2.7 Analog port input IAIN current Analog input voltage -- -- Reference voltage -- Power supply current Reference voltage supply current Interchannel disparity IA IAS*2 IR IRS*2 -- -- AN0 to AN7 AVRL AVRL + 2.7 AVRH AVRH - AVRL 2.7 AVRL 0 AVCC = 3.3 V 0.3 V -- AVCC -- AVCC = 3.3 V 0.15 V AVCC = 3.3 V -- -- Stop mode -- AVRH AVCC = 3.3 V Stop mode AVRH -- AN0 to AN3, AN5 to AN7 -- -- 9 8 5 1.5 5 4 *1: When FC = 50 MHz (frequency), and the machine cycle is 4.0 ns. The minimum value of the ADCT resister is #A224, differs from that of the MB90F243. *2: Current when the A/D converter is not operating and the CPU is stopped. Notes: * The smaller | AVRH - AVRL |, the greater the error would become relatively. * If the output impedance of the external circuit for the analog input is high, sampling period might be insufficient. When the sampling period set at near the minimum value, the output impedance of the external circuit should be less than approximately 300 . 40 MB90F244 * Analog input circuit model diagram CO = Approx. 60 pF RON1 Analog input pin Approx. 300 AVRH Be switched on, only while A/D conversion is performed. RON2 Approx. C1 150 Approx. 4 pF Comparator Comparator * * * Comparator AVRL Note: Use the values shows as reference only. 41 MB90F244 6. A/D Converter Glossary * Resolution Analog changes that are identifiable with the A/D converter. When the number of bits is 10, analog voltage can be divide into 210 . * Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics * Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value * Total error (unit: LSB) The difference between theoretical and actual conversion values caused by the zero transition error, full-scale transition error, non-linearity error, differential linearity error, and noise Digital output 11 1111 1111 11 1111 1110 * * * * * * * * * * * * * * * * * (1 LSB x N + VOT) Linearity error 00 0000 0010 00 0000 0001 00 0000 0000 VOT VNT V(N + 1)T VFST Analog input 1 LSB = VFST - VOT [V] 1022 VNT - (1 LSB x N + VOT) Digital output N [LSB] linearity error = 1 LSB V(N+1)T - VNT Digital output N = - 1 LSB [LSB] differential linearity error 1 LSB VOT: Voltage for digital output transit from "000H" to "001H" VFST: Voltage for digital output transit from "3FEH" to "3FFH" 42 MB90F244 s INSTRUCTIONS (412 INSTRUCTIONS) Table 1 Item Mnemonic Explanation of Items in Table of Instructions Explanation Upper-case letters and symbols: Represented as they appear in assembler Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction. Indicates the number of bytes. Indicates the number of cycles. See Table 4 for details about meanings of letters in items. Indicates the correction value for calculating the number of actual cycles during execution of instruction. The number of actual cycles during execution of instruction is summed with the value in the "cycles" column. Indicates operation of instruction. Indicates special operations involving the bits 15 through 08 of the accumulator. Z: Transfers "0". X: Extends before transferring. --: Transfers nothing. Indicates special operations involving the high-order 16 bits in the accumulator. *: Transfers from AL to AH. --: No transfer. Z: Transfers 00H to AH. X: Transfers 00H or FFH to AH by extending AL. Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). *: Changes due to execution of instruction. --: No change. S: Set by execution of instruction. R: Reset by execution of instruction. # ~ B Operation LH AH I S T N Z V C RMW Indicates whether the instruction is a read-modify-write instruction (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.). *: Instruction is a read-modify-write instruction --: Instruction is not a read-modify-write instruction Note: Cannot be used for addresses that have different meanings depending on whether they are read or written. 43 MB90F244 Table 2 Symbol A Explanation of Symbols in Table of Instructions Explanation 32-bit accumulator The number of bits used varies according to the instruction. Byte: Low order 8 bits of AL Word: 16 bits of AL Long: 32 bits of AL, AH High-order 16 bits of A Low-order 16 bits of A Stack pointer (USP or SSP) Program counter Stack pointer upper limit register Stack pointer lower limit register Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Compact direct addressing Direct addressing Physical direct addressing Bits 0 to 15 of addr24 Bits 16 to 23 of addr24 I/O area (000000H to 0000FFH) AH AL SP PC SPCU SPCL PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 addr24 0 to 15 addr24 16 to 23 io (Continued) 44 MB90F244 (Continued) Symbol #imm4 #imm8 #imm16 #imm32 ext (imm8) disp8 disp16 bp vct4 vct8 ( )b rel ear eam rlst Explanation 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset value Vector number (0 to 15) Vector number (0 to 255) Bit address Branch specification relative to PC Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list 45 MB90F244 Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Notation RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Fields Address format Register direct "ea" corresponds to byte, word, and long-word types, starting from the left Number of bytes in address extemsion* -- @RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + dip16 addr16 Register indirect 0 Register indirect with post-increment 0 Register indirect with 8-bit displacement 1 Register indirect with 16-bit displacemen 2 Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address 0 0 2 2 * : The number of bytes for address extension is indicated by the "+" symbol in the "#" (number of bytes) column in the Table of Instructions. 46 MB90F244 Table 4 Code 00 to 07 Number of Execution Cycles for Each Form of Addressing Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + dip16 @addr16 (a)* Number of execution cycles for each from of addressing Listed in Table of Instructions 08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F 1 4 1 1 2 2 2 1 * : "(a)" is used in the "cycles" (number of cycles) column and column B (correction value) in the Table of Instructions. Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles Operand Internal register Internal RAM even address Internal RAM odd address Even address not in internal RAM Odd address not in internal RAM External data bus (8 bits) + + + + + + (b)* byte 0 0 0 1 1 1 + + + + + + (c)* word 0 0 1 1 3 3 + + + + + + (d)* long 0 0 2 2 6 6 * : "(b)", "(c)", and "(d)" are used in the "cycles" (number of cycles) column and column B (correction value) in the Table of Instructions. 47 MB90F244 Table 6 Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVP MOVP MOVN A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, @SP+disp8 A, addr24 A, @A A, #imm4 # ~ Transfer Instructions (Byte) [50 Instructions] B (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) (b) (b) (b) 0 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 (b) 0 (b) (b) 0 (b) (b) Operation byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RLi))+disp8) byte (A) ((SP)+disp8) byte (A) (addr24) byte (A) ((A)) byte (A) imm4 byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RWi))+disp8) byte (A) ((RLi))+disp8) byte (A) ((SP)+disp8) byte (A) (addr24) byte (A) ((A)) byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) byte ((RLi)) +disp8) (A) byte ((SP)+disp8) (A) byte (addr24) (A) byte (Ri) (ear) byte (Ri) (eam) byte ((A)) (Ri) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 byte ((A)) (AH) LH AH I S T N Z V C RMW 2 2 2 3 1 1 1 2 2+ 2+ (a) 2 2 2 2 2 2 6 3 3 3 3 5 2 2 1 1 Z Z Z Z Z Z Z Z Z Z Z Z Z X X X X X X X X X X X X X - - - - - - - - - - - - - - - - - - - - * * * * * * * - * * * - * * * * * * * * - * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * R * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2 2 MOVX A, dir 2 3 MOVX A, addr16 1 2 MOVX A, Ri 1 2 MOVX A, ear 2+ 2+ (a) MOVX A, eam 2 2 MOVX A, io 2 2 MOVX A, #imm8 2 2 MOVX A, @A 3 MOVX A,@RWi+disp8 2 6 MOVX A, @RLi+disp8 3 3 3 MOVX A, @SP+disp8 3 5 MOVPX A, addr24 2 2 MOVPX A, @A MOV MOV MOV MOV MOV MOV MOV MOV MOVP MOV MOV MOVP MOV MOV MOV MOV MOV MOV MOV MOV dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A @SP+disp8, A addr24, A Ri, ear Ri, eam @A, Ri ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH 2 2 2 3 1 1 2 2 2+ 2+ (a) 2 2 6 3 3 3 3 5 2 2 2+ 3+ (a) 3 2 3 2 2+ 3+ (a) 2 2 3 3 3 3 2 3 3+ 2+ (a) 2 2 (Continued) 48 MB90F244 (Continued) Mnemonic XCH XCH XCH XCH A, ear A, eam Ri, ear Ri, eam # ~ B Operation byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam) LH AH I S T N Z V C RMW 2 3 0 2+ 3+ (a) 2x (b) 2 4 0 2+ 5+ (a) 2x (b) Z Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - For an explanation of "(a)" and "(b)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 49 MB90F244 Table 7 Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 A, @SP+disp8 # ~ Transfer Instructions (Word) [40 Instructions] B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) (c) (c) (c) 0 0 0 0 (c) (c) (c) (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) Operation word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16 word (A) ((RWi) +disp8) word (A) ((RLi) +disp8) word (A) ((SP) +disp8 word (A) (addr24) word (A) ((A)) word (dir) (A) word (addr16) (A) word (SP) imm16 word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) word ((RWi) +disp8) (A) word ((RLi) +disp8) (A) word ((SP) +disp8) (A) word (addr24) (A) word ((A)) (RWi) word (RWi) (ear) word (RWi) (eam) word (ear) (RWi) word (eam) (RWi) word (RWi) imm16 word (io) imm16 word (ear) imm16 word (eam) imm16 word ((A)) (AH) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) LH AH I S T N Z V C RMW MOVPWA, addr24 MOVPWA, @A 2 2 3 2 1 2 1 1 2 1 2+ 2+ (a) 2 2 2 2 3 2 2 3 3 6 3 3 5 3 2 2 2 3 4 1 1 2 2+ 2 2 3 3 5 2 2 2+ 2 2+ 3 4 4 4+ 2 2 2 2 2 1 2 2+ (a) 2 3 6 3 3 3 2 3+ (a) 3 3+ (a) 2 3 2 2+ (a) 2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * - * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW dir, A addr16, A SP # imm16 , SP A , RWi, A ear, A eam, A io, A @RWi+disp8, A @RLi+disp8, A @SP+disp8, A RWi, ear RWi, eam ear, RWi eam, RWi RWi, #imm16 io, #imm16 ear, #imm16 eam, #imm16 MOVPWaddr24, A MOVPW@A, RWi MOVW @AL, AH XCHW XCHW XCHW XCHW A, ear A, eam RWi, ear RWi, eam 2 3 0 2+ 3+ (a) 2x (c) 2 4 0 2+ 5+ (a) 2x (c) Note: For an explanation of "(a)" and "(c)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 50 MB90F244 Table 8 Mnemonic # Transfer Instructions (Long Word) [11 Instructions] ~ B 0 (d) 0 (d) (d) (d) (d) (d) (d) 0 (d) Operation long (A) (ear) long (A) (eam) long (A) imm32 long (A) ((SP) +disp8) long (A) (addr24) long (A) ((A)) long ((A)) (RLi) long ((SP) + disp8) (A) long (addr24) (A) long (ear) (A) long (eam) (A) LH AH I S T N Z V C RMW MOVL A, ear 2 1 MOVL A, eam 2+ 3+ (a) MOVL A, # imm32 5 3 MOVL A, @SP + disp8 3 4 MOVPL A, addr24 5 4 MOVPL A, @A 2 3 MOVPL@A, RLi 2 5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - MOVL @SP + disp8, A 3 4 MOVPL addr24, A 5 4 MOVL ear, A 2 2 MOVL eam, A 2+ 3+ (a) For an explanation of "(a)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 51 MB90F244 Table 9 Mnemonic ADD A, #imm8 ADD A, dir ADD A, ear ADD A, eam ADD ear, A ADD eam, A ADDC A ADDC A, ear ADDC A, eam ADDDC A SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] # ~ B Operation byte (A) (A) + imm8 byte (A) (A) + (dir) byte (A) (A) + (ear) byte (A) (A) + (eam) byte (ear) (ear) + (A) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) byte (A) (A) + (ear) + (C) byte (A) (A) + (eam) + (C) byte (A) (AH) + (AL) + (C) (Decimal) byte (A) (A) - imm8 byte (A) (A) - (dir) byte (A) (A) - (ear) byte (A) (A) - (eam) byte (ear) (ear) - (A) byte (eam) (eam) - (A) byte (A) (AH) - (AL) - (C) byte (A) (A) - (ear) - (C) byte (A) (A) - (eam) - (C) byte (A) (AH) - (AL) - (C) (Decimal) word (A) (AH) + (AL) word (A) (A) + (ear) word (A) (A) + (eam) word (A) (A) + imm16 word (ear) (ear) + (A) word (eam) (eam) + (A) word (A) (A) + (ear) + (C) word (A) (A) + (eam) + (C) word (A) (AH) - (AL) word (A) (A) - (ear) word (A) (A) - (eam) word (A) (A) - imm16 word (ear) (ear) - (A) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) word (A) (A) - (eam) - (C) long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) + imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) - imm32 LH AH I S T N Z V C RMW 2 2 0 2 3 (b) 2 2 0 2+ 3+ (a) (b) 2 2 0 2+ 3+ (a) 2x (b) 1 2 0 2 2 0 2+ 3+ (a) (b) 1 3 0 2 2 0 2 3 (b) 2 2 0 2+ 3+ (a) (b) 2 2 0 2+ 3+ (a) 2x (b) 1 2 0 2 2 0 2+ 3+ (a) (b) 1 3 0 Z Z Z Z - Z Z Z Z Z Z Z Z Z - - Z Z Z Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - * * - - - - - - - - * * - - - - - - - - * * - - - - - - * * - - - - - - - - ADDW A 1 2 0 ADDW A, ear 2 2 0 ADDW A, eam 2+ 3+ (a) (c) ADDW A, #imm16 3 2 0 ADDW ear, A 2 2 0 ADDW eam, A 2+ 3+ (a) 2x (c) ADDCW A, ear 2 2 0 ADDCW A, eam 2+ 3+ (a) (c) SUBW A 1 2 0 SUBW A, ear 2 2 0 SUBW A, eam 2+ 3+ (a) (c) SUBW A, #imm16 3 2 0 SUBW ear, A 2 2 0 SUBW eam, A 2+ 3+ (a) 2x (c) SUBCW A, ear 2 2 0 SUBCW A, eam 2+ 3+ (a) (c) ADDL ADDL ADDL SUBL SUBL SUBL A, ear 2 5 A, eam 2+ 6+ (a) A, #imm32 5 4 A, ear 2 5 A, eam 2+ 6+ (a) A, #imm32 5 4 0 (d) 0 0 (d) 0 For an explanation of "(a)", "(b)", "(c)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 52 MB90F244 Table 10 Mnemonic INC INC DEC DEC INCW INCW ear eam ear eam ear eam Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] # ~ B Operation LH AH I S T N Z V C RMW 2 2 0 byte (ear) (ear) +1 2+ 3+ (a) 2x (b) byte (eam) (eam) +1 2 2 0 byte (ear) (ear) -1 2+ 3+ (a) 2x (b) byte (eam) (eam) -1 2 2 0 word (ear) (ear) +1 2+ 3+ (a) 2x (c) word (eam) (eam) +1 2 2 0 word (ear) (ear) -1 2+ 3+ (a) 2x (c) word (eam) (eam) -1 2 4 0 long (ear) (ear) +1 2+ 5+ (a) 2x (d) long (eam) (eam) +1 2 4 0 long (ear) (ear) -1 2+ 5+ (a) 2x (d) long (eam) (eam) -1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - - - - - - - * * * * * * * * * * * * DECW ear DECW eam INCL INCL DECL DECL ear eam ear eam For an explanation of "(a)", "(b)", "(c)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 11 Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW A A, ear A, eam A, #imm8 A A, ear A, eam A, #imm16 # Compare Instructions (Byte/Word/Long Word) [11 Instructions] ~ B 0 0 (b) 0 0 0 (c) 0 0 (d) 0 Operation byte (AH) - (AL) byte (A) - (ear) byte (A) - (eam) byte (A) - imm8 word (AH) - (AL) word (A) - (ear) word (A) - (eam) word (A) - imm16 long (A) - (ear) long (A) - (eam) long (A) - imm32 LH AH I S T N Z V C RMW 1 2 2 2 2+ 2+ (a) 2 2 1 2 2 2 2+ 2+ (a) 3 2 2 3 2+ 4+ (a) 5 3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - - - - - - CMPL A, ear CMPL A, eam CMPL A, #imm32 For an explanation of "(a)", "(b)", "(c)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 53 MB90F244 Table 12 Mnemonic DIVU DIVU DIVU A A, ear Unsigned Multiplication and Division Instructions (Word/Long Word) [11 Instructions] # 1 2 ~ * 1 B Operation LH AH I S T N Z V C RMW *2 *3 *4 *5 A, eam 2+ DIVUW A, ear DIVUW 2 A, eam 2+ 0 word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * - - - - - - * * * * * - - - - - - - - - - - - - - - - - MULU MULU MULU MULUW MULUW MULUW A A, ear A, eam A A, ear A, eam 1 2 2+ 1 2 2+ *8 *9 *10 *11 *12 *13 0 0 (b) 0 0 (c) byte (AH) x byte (AL) word (A) byte (A) x byte (ear) word (A) byte (A) x byte (eam) word (A) word (AH) x word (AL) long (A) word (A) x word (ear) long (A) word (A) x word (eam) long (A) For an explanation of "(b)" and "(c), refer to Table 5, "Correction Values for Number of Cycle Used to Calculate Number of Actual Cycles." *1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13: 3 when dividing into zero, 6 when an overflow occurs, and 14 normally. 3 when dividing into zero, 5 when an overflow occurs, and 13 normally. 5 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 17 + (a) normally. 3 when dividing into zero, 5 when an overflow occurs, and 21 normally. 4 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 25 + (a) normally. (b) when dividing into zero or when an overflow occurs, and 2 x (b) normally. (c) when dividing into zero or when an overflow occurs, and 2 x (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not 0. 3 when byte (ear) is zero, and 7 when byte (ear) is not 0. 4 + (a) when byte (eam) is zero, and 8 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not 0. 3 when word (ear) is zero, and 11 when word (ear) is not 0. 4 + (a) when word (eam) is zero, and 12 + (a) when word (eam) is not 0. 54 MB90F244 Table 13 Mnemonic DIV DIV DIV Signed Multiplication and Division Instructions (Word/Long Word) [11 Insturctions] # 2 2 ~ * 1 B Operation LH AH I S T N Z V C RMW A A, ear *2 *3 *4 *5 *8 *9 *10 *11 *12 *13 A, eam 2+ DIVW A, ear DIVW 2 A, eam 2+ 0 word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam) 0 0 (b) 0 0 (b) byte (AH) x byte (AL) word (A) byte (A) x byte (ear) word (A) byte (A) x byte (eam) word (A) word (AH) x word (AL) long (A) word (A) x word (ear) long (A) word (A) x word (eam) long (A) Z Z Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * - - - - - - * * * * * - - - - - - - - - - - - - - - - - MUL MUL 2 2 MUL A, eam 2+ MULW A 2 MULW A, ear 2 MULW A, eam 2+ A A, ear For an explanation of "(b)" and "(c)", refer to Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." *1: *2: *3: *4: *5: 3 when dividing into zero, 8 or 18 when an overflow occurs, and 18 normally. 3 when dividing into zero, 10 or 21 when an overflow occurs, and 22 normally. 4 + (a) when dividing into zero, 11 + (a) or 22 + (a) when an overflow occurs, and 23 + (a) normally. When the dividend is positive: 4 when dividing into zero, 10 or 29 when an overflow occurs, and 30 normally. When the dividend is negative: 4 when dividing into zero, 11 or 30 when an overflow occurs, and 31 normally. When the dividend is positive: 4 + (a) when dividing into zero, 11 + (a) or 30 + (a) when an overflow occurs, and 31 + (a) normally. When the dividend is negative: 4 + (a) when dividing into zero, 12 + (a) or 31 + (a) when an overflow occurs, and 32 + (a) normally. (b) when dividing into zero or when an overflow occurs, and 2 x (b) normally. (c) when dividing into zero or when an overflow occurs, and 2 x (c) normally. 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. *6: *7: *8: *9: *10: *11: *12: *13: Note: Which of the two values given for the number of execution cycles applies when an overflow error occurs in a DIV or DIVW instruction depends on whether the overflow was detected before or after the operation. 55 MB90F244 Table 14 Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW NOTW NOTW NOTW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam A A, #imm16 A, ear A, eam ear, A eam, A A A, #imm16 A, ear A, eam ear, A eam, A A A, #imm16 A, ear A, eam ear, A eam, A A ear eam # ~ Logical 1 Instructions (Byte, Word) [39 Instructions] B Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A) byte (A) not (A) byte (ear) not (ear) byte (eam) not (eam) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A) word (A) not (A) word (ear) not (ear) word (eam) not (eam) LH AH I S T N Z V C RMW 2 2 0 2 2 0 2+ 3+ (a) (b) 2 3 0 2+ 3+ (a) 2x (b) 2 2 0 2 2 0 2+ 3+ (a) (b) 2 3 0 2+ 3+ (a) 2x (b) 2 2 0 2 2 0 2+ 3+ (a) (b) 2 3 0 2+ 3+ (a) 2x (b) 1 2 0 2 2 0 2+ 3+ (a) 2x (b) 1 2 0 3 2 0 2 2 0 2+ 3+ (a) (c) 2 3 0 2+ 3+ (a) 2x (c) 1 2 0 3 2 0 2 2 0 2+ 3+ (a) (c) 2 3 0 2+ 3+ (a) 2x (c) 1 2 0 3 2 0 2 2 0 2+ 3+ (a) (c) 2 3 0 2+ 3+ (a) 2x (c) 1 2 0 2 2 0 2+ 3+ (a) 2x (c) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * - - - * * - - - * * - * * - - - - * * - - - - * * - - - - * * - * * For an explanation of "(a)", "(b)", "(c)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 56 MB90F244 Table 15 Mnemonic ANDL A, ear ANDL A, eam ORL ORL A, ear A, eam # ~ Logical 2 Instructions (Long Word) [6 Instructions] B 0 (d) 0 (d) 0 (d) Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam) LH AH I S T N Z V C RMW 2 5 2+ 6+ (a) 2 5 2+ 6+ (a) 2 5 2+ 6+ (a) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * R R R R R R - - - - - - - - - - - - XORL A, ear XORL A, eam For an explanation of "(a)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 16 Mnemonic NEG NEG NEG A ear eam # 1 ~ 2 Sign Inversion Instructions (Byte/Word) [6 Instructions] B 0 Operation byte (A) 0 - (A) LH AH I S T N Z V C RMW X - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * - * * - * * 2 2 0 byte (ear) 0 - (ear) 2+ 3+ (a) 2x (b) byte (eam) 0 - (eam) 1 2 0 word (A) 0 - (A) NEGW A NEGW ear NEGW eam 2 2 0 word (ear) 0 - (ear) 2+ 3+ (a) 2x (c) word (eam) 0 - (eam) For an explanation of "(a)", "(b)" and "(c)" and refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 17 Mnemonic ABS A ABSW A ABSL A # 2 2 2 Absolute Value Instructions (Byte/Word/Long Word) [3 Insturctions] ~ 2 2 4 B 0 0 0 Operation byte (A) absolute value (A) word (A) absolute value (A) long (A) absolute value (A) LH AH I S T N Z V C RMW Z - - - - - - - - - - - - - - * * * * * * * * * - - - - - - Table 18 Mnemonic NRML A, R0 # 2 ~ * B 0 Normalize Instructions (Long Word) [1 Instruction] Operation long (A) Shifts to the position at which "1" was set first byte (R0) current shift count LH AH I S T N Z V C RMW - - - - * - - - - - * : 5 when the contents of the accumulator are all zeroes, 5 + (R0) in all other cases. 57 MB90F244 Table 19 Mnemonic RORC A ROLC A RORC RORC ROLC ROLC ASR LSR LSL ASR LSR LSL Shift Instructions (Byte/Word/Long Word) [27 Instructions] B 0 0 Operation byte (A) Right rotation with carry byte (A) Left rotation with carry byte (ear) Right rotation with carry byte (eam) Right rotation with carry byte (ear) Left rotation with carry byte (eam) Left rotation with carry byte (A) Arithmetic right barrel shift (A, R0) byte (A) Logical right barrel shift (A, R0) byte (A) Logical left barrel shift (A, R0) byte (A) Arithmetic right barrel shift (A, imm8) byte (A) Logical right barrel shift (A, imm8) byte (A) Logical left barrel shift (A, imm8) LH AH I S T N Z V C RMW # 2 2 ~ 2 2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * - * * - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * * * * - - - - - - - - - - - - - - - - - - - - - ear eam ear eam A, R0 A, R0 A, R0 2 2 0 2+ 3+ (a) 2x (b) 2 2 0 2+ 3+ (a) 2x (b) 2 2 2 *1 *1 *1 *3 *3 *3 2 2 2 *1 *1 *1 *3 *3 *3 *2 *2 *2 *4 *4 *4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A, #imm8 3 A, #imm8 3 A, #imm8 3 ASRW A 1 LSRW A/SHRW A 1 LSLW A/SHLW A 1 word (A) Arithmetic right shift (A, 1 bit) word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit) ** *R -* * * - * * - * * - * * - * * * * * * * * * * * * ASRW A, R0 LSRW A, R0 LSLW A, R0 2 2 2 word (A) Arithmetic right barrel shift (A, R0) - word (A) Logical right barrel shift (A, R0) - word (A) Logical left barrel shift (A, R0) - word (A) Arithmetic right barrel shift (A, imm8) word (A) Logical right barrel shift (A, imm8) ASRW A, #imm8 3 LSRW A, #imm8 3 LSLW A, #imm8 3 word (A) Logical left barrel shift (A, imm8) - - - ASRL A, R0 LSRL A, R0 LSLL A, R0 ASRL LSRL LSLL 2 2 2 long (A) Arithmetic right shift (A, R0) - long (A) Logical right barrel shift (A, R0) - long (A) Logical left barrel shift (A, R0) - long (A) Arithmetic right shift (A, imm8) - long (A) Logical right barrel shift (A, imm8) - long (A) Logical left barrel shift (A, imm8) - A, #imm8 3 A, #imm8 3 A, #imm8 3 For an explanation of "(a)" and "(b)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." *1: *2: *3: *4: 3 when R0 is 0, 3 + (R0) in all other cases. 3 when R0 is 0, 4 + (R0) in all other cases. 3 when imm8 is 0, 3 + (imm8) in all other cases. 3 when imm8 is 0, 4 + (imm8) in all other cases. 58 MB90F244 Table 20 Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP rel rel rel rel # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 ~ * *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 2 3 4+ (a) 3 4+ (a) 3 1 Branch 1 Instructions [31 Instructions] Operation Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0 ( (V) xor (N) ) or (Z) = 1 ( (V) xor (N) ) or (Z) = 0 Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam) word (PC) (ear), (PCB) (ear +2) word (PC) (eam), (PCB) (eam +2) word (PC) ad24 0 to 15 (PCB) ad24 16 to 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call linstruction word (PC) (ear) 0 to 15, (PCB) (ear) 16 to 23 word (PC) (eam) 0 to 15, (PCB) (eam) 16 to 23 word (PC) addr 0 to 15, (PCB) addr 16 to 23 LH AH I S T N Z V C RMW B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @A addr16 @ear @eam @ear *3 @eam *3 addr24 @ear *4 2 @eam *4 2+ addr16 *5 3 1 #vct4 *5 2 @ear *6 2+ 4 4 (c) 5+ (a) 2x (c) 5 (c) 5 2x (c) 7 2x (c) 8+ (a) 7 *2 2x (c) CALLP @eam *6 CALLP addr24 *7 For an explanation of "(a)", "(c)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." *1: *2: *3: *4: *5: *6: *7: 3 when branching, 2 when not branching. 3 x (c) + (b) Read (word) branch address. W: Save (word) to stack; R: Read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: Read (long word) branch address. Save (long word) to stack. 59 MB90F244 Table 21 Mnemonic # ~ * *1 *1 *3 *1 *3 *2 *4 *2 *4 14 12 13 14 9 11 6 1 Branch 2 Instructions [20 Instructions] Operation Branch when byte (A) imm8 Branch when byte (A) imm16 Branch when byte (ear) imm8 Branch when byte (eam) imm8 Branch when word (ear) imm16 Branch when word (eam) imm16 LH AH I S T N Z V C RMW B 0 0 0 (b) 0 (c) 0 CBNE A, #imm8, rel 3 CWBNE A, #imm16, rel 4 CBNE CBNE CWBNE CWBNE ear, #imm8, rel eam, #imm8, rel ear, #imm16, rel eam, #imm16, rel - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - R R R R * * - - - - - - - - - - - S S S S * * - - - - - - - - - - - - - - - * * - * * * * * * * * * * - - - - * * - * * * * * * * * * * - - - - * * - * * * * * * * * * * - - - - * * - * * * * * * - - - - - - - - * * - - - - - - - - * - * - - - - - - - 4 4+ 5 5+ 3 3+ 3 3+ 2 3 4 1 1 2 2 DBNZ DBNZ ear, rel eam, rel DWBNZ ear, rel DWBNZ eam, rel INT #vct8 INT addr16 INTP addr24 INT9 RETI RETIQ *6 LINK #imm8 Branch when byte (ear) = (ear) - 1, and (ear) 0 2x (b) Branch when byte (ear) = (eam) - 1, and (eam) 0 0 Branch when word (ear) = (ear) - 1, and (ear) 0 2x (c) Branch when word (eam) = (eam) - 1, and (eam) 0 8x (c) 6x (c) 6x (c) 8x (c) 6x (c) *5 (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt Return from interrupt At constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve old frame pointer from stack. Return from subroutine Return from subroutine 5 UNLINK RET *7 RETP *8 1 4 5 1 1 (c) (d) (c) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - For an explanation of "(b)", "(c)" and "(d)", refer to Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." *1: *2: *3: *4: *5: *6: 4 when branching, 3 when not branching 5 when branching, 4 when not branching 5 + (a) when branching, 4 + (a) when not branching 6 + (a) when branching, 5 + (a) when not branching 3 x (b) + 2 x (c) when an interrupt request is generated, 6 x (c) when returning from the interrupt. High-speed interrupt return instruction. When an interrupt request is detected during this instruction, the instruction branches to the interrupt vector without performing stack operations when the interrupt is generated. *7: Return from stack (word) *8: Return from stack (long word) 60 MB90F244 Table 22 Mnemonic PUSHW PUSHW PUSHW PUSHW POPW POPW POPW POPW JCTX AND OR A AH PS rlst A AH PS rlst @A # 1 1 1 2 1 1 1 2 1 Other Control Instructions (Byte/Word/Long Word) [36 Instructions] ~ 3 3 3 *3 3 3 3 *2 9 3 3 2 2 B (c) (c) (c) *4 (c) (c) (c) *4 Operation word (SP) (SP) -2, ((SP)) (A) word (SP) (SP) -2, ((SP)) (AH) word (SP) (SP) -2, ((SP)) (PS) (SP) (SP) -2n, ((SP)) (rlst) word (A) ((SP)), (SP) (SP) +2 word (AH) ((SP)), (SP) (SP) +2 word (PS) ((SP)), (SP) (SP) +2 (rlst) ((SP)) , (SP) (SP) LH AH I S T N Z V C RMW - - - - - - - - - - - - - * - - - - - - - - - - * * - - * - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - * * * - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - * * * - - - - - - - - - - - * * * - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 6x (c) Context switch instruction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR, #imm8 2 CCR, #imm8 2 2 2 byte (CCR) (CCR) and imm8 - - byte (CCR) (CCR) or imm8 byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam word (SP) ext (imm8) word (SP) imm16 byte (A) (brgl) byte (brg2) (A) byte (brg2) imm8 No operation Prefix code for AD space access Prefix code for DT space access Prefix code for PC space access Prefix code for SP space access MOV RP #imm8 , MOV ILM, #imm8 MOVEA RWi, ear MOVEA RWi, eam MOVEA A, ear MOVEA A, eam ADDSP #imm8 ADDSP #imm16 MOV MOV MOV - - - - - - - - Z - - - - - - - - - - - - - Z Z Z 2 3 2+ 2+ (a) 2 2 2+ 1+ (a) 2 3 2 2 3 1 1 1 1 1 1 1 3 3 *1 1 2 1 1 1 1 1 1 1 2 2 2 2 *5 *6 *7 A, brgl brg2, A brg2, #imm8 NOP ADB DTB PCB SPB NCC CMR Prefix code for no flag change Prefix code for the common register bank MOVW SPCU, #imm16 4 MOVW SPCL, #imm16 4 SETSPC CLRSPC BTSCN A BTSCNSA BTSCNDA 2 2 2 2 2 word (SPCU) (imm16) word (SPCL) (imm16) Stack check operation enable Stack check operation disable byte (A) position of "1" bit in word (A) byte (A) position of "1" bit in word (A) x 2 byte (A) position of "1" bit in word (A) x 4 For an explanation of "(a)" and "(c)", refer to Tables 4 and 5. *1: PCB, ADB, SSB, USB, and SPB: 1 cycle DTB: 2 cycles DPR: 3 cycles *2: 3 + 4 x (pop count) *3: 3 + 4 x (push count) *4: *5: *6: *7: Pop count x (c), or push count x (c) 3 when AL is 0, 5 when AL is not 0. 4 when AL is 0, 6 when AL is not 0. 5 when AL is 0, 7 when AL is not 0. 61 MB90F244 Table 23 Mnemonic MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A SETB SETB SETB CLRB CLRB CLRB BBC BBC BBC BBS BBS BBS SBBS dir:bp addr16:bp io:bp dir:bp addr16:bp io:bp dir:bp, rel addr16:bp, rel io:bp, rel dir:bp, rel addr16:bp, rel io:bp, rel addr16:bp, rel # 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 ~ 3 3 3 4 4 4 4 4 4 4 4 4 *1 *1 *1 *1 *1 *1 *2 *3 *3 Bit Manipulation Instructions [21 Instructions] B (b) (b) (b) Operation byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b LH AH I S T N Z V C RMW Z Z Z - - - - - - - - - - - - - - - - - - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * - - - - - - - - - - - - - - - * * * * * * - - - - - - * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * - - - - - - * - - 2x (b) bit (dir:bp) b (A) 2x (b) bit (addr16:bp) b (A) 2x (b) bit (io:bp) b (A) 2x (b) bit (dir:bp) b 1 2x (b) bit (addr16:bp) b 1 2x (b) bit (io:bp) b 1 2x (b) bit (dir:bp) b 0 2x (b) bit (addr16:bp) b 0 2x (b) bit (io:bp) b 0 (b) (b) (b) (b) (b) (b) 2x (b) *4 *4 Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1 Branch when (addr16:bp) b = 1, bit = 1 WBTS io:bp WBTC io:bp Wait until (io:bp) b = 1 Wait until (io:bp) b = 0 For an explanation of "(b)", refer to Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." *1: *2: *3: *4: 5 when branching, 4 when not branching 7 when condition is satisfied, 6 when not satisfied Undefined count Until condition is satisfied 62 MB90F244 Table 24 Mnemonic SWAP SWAPW EXT EXTW ZEXT ZEXTW # 1 1 1 1 1 1 Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] ~ 3 2 1 2 1 2 B 0 0 0 0 0 0 Operation byte (A) 0 to 7 (A) 8 to 15 word (AH) (AL) Byte code extension Word code extension Byte zero extension Word zero extension LH AH I S T N Z V C RMW - - X - Z - - * - X - Z - - - - - - - - - - - - - - - - - - - - * * R R - - * * * * - - - - - - - - - - - - - - - - - - Table 25 Mnemonic MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FILS/FILSI MOVSW/MOVSWI String Instructions [10 Instructions] Operation LH AH I S T N Z V C RMW # 2 2 2 2 ~ *2 *2 *1 *1 B *3 Byte transfer @AH+ @AL+, counter = RW0 - *3 Byte transfer @AH- @AL-, counter = RW0 - *4 Byte retrieval @AH+ - AL, counter = RW0 *4 Byte retrieval @AH- - AL, counter = RW0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * - - * * * - - * * * - - * * * - - * * - - - * * - - - * * - - - * * - - - - - - - - - - - 2 5m +3 *5 Byte filling @AH+ AL, counter = RW0 2 2 2 2 *2 *2 *1 *1 *6 Word transfer @AH+ @AL+, counter = RW0 *6 Word transfer @AH- @AL-, counter = RW0 *7 Word retrieval @AH+ - AL, counter = RW0 *7 Word retrieval @AH- - AL, counter = RW0 MOVSWD SCWEQ/SCWEQI SCWEQD FILSW/FILSWI 2 5m +3 *8 Word filling @AH+ AL, counter = RW0 m: RW0 value (counter value) *1: *2: *3: *4: *5: *6: *7: *8: 3 when RW0 is 0, 2 + 6 x (RW0) for count out, and 6n + 4 when match occurs 4 when RW0 is 0, 2 + 6 x (RW0) in any other case (b) x (RW0) (b) x n (b) x (RW0) (c) x (RW0) (c) x n (c) x (RW0) 63 MB90F244 Table 26 Mnemonic @A, @RLi, #imm8 @A, eam, #imm8 addr16, @RLi, #imm8 addr16, eam, #imm8 @A, @RLi, #imm8 @A, eam, #imm8 addr16, @RLi, #imm8 addr16, eam, #imm8 @RLi, @A, #imm8 eam, @A, #imm8 @RLi, addr16, #imm8 eam, addr16, #imm8 @RLi, @A, #imm8 eam, @A, #imm8 @RLi, addr16, #imm8 eam, addr16, #imm8 bnk : addr16, *5 bnk : addr16, #imm8 MOVMW bnk : addr16, *5 bnk : addr16, #imm8 MOVM MOVM MOVM MOVM MOVMW MOVMW MOVMW MOVMW MOVM MOVM MOVM MOVM MOVMW MOVMW MOVMW MOVMW MOVM Multiple Data Transfer Instructions [18 Instructions] B * *3 *3 *3 *4 *4 *4 *4 *3 *3 *3 *3 *4 *4 *4 *4 *3 *4 3 # 3 3+ 5 5+ 3 3+ 5 5+ 3 3+ 5 5+ 3 3+ 5 5+ 7 7 ~ * *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *1 1 Operation Multiple data trasfer byte ((A)) ((RLi)) Multiple data trasfer byte ((A)) (eam) Multiple data trasfer byte (addr16) ((RLi)) Multiple data trasfer byte (addr16) (eam) Multiple data trasfer word ((A)) ((RLi)) Multiple data trasfer word ((A)) (eam) Multiple data trasfer word (addr16) ((RLi)) Multiple data trasfer word (addr16) (eam) Multiple data trasfer byte ((RLi)) ((A)) Multiple data trasfer byte (eam) ((A)) Multiple data transfer byte ((RLi)) (addr16) Multiple data transfer byte (eam) (addr16) LH AH I S T N Z V C RMW Multiple data trasfer word ((RLi)) ((A)) Multiple data trasfer word (eam) ((A)) Multiple data transfer word ((RLi)) (addr16) Multiple data transfer word (eam) (addr16) Multiple data transfer byte (bnk:addr16) (bnk:addr16) Multiple data transfer word (bnk:addr16) (bnk:addr16) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - *1: 5 + imm8 x 5, 256 times when imm8 is zero. *2: 5 + imm8 x 5 + (a), 256 times when imm8 is zero. *3: Number of transfers x (b) x 2 *4: Number of transfers x (c) x 2 *5: The bank register specified by "bnk" is the same as for the MOVS instruction. 64 MB90F244 s ORDERING IMFORMATION Part number MB90F244PFT-G Package 80-pin Plastic TQFP (FPT-80P-M15) Remarks 65 MB90F244 s PACKAGE DIMENSIONS 80-pin Plastic TQFP (FPT-80P-M15) 14.000.20(.551.008)SQ 12.000.10(.472.004)SQ 60 41 0.145 -0.03 +.002 .006 -.001 +0.05 61 40 80 21 Details of "A" part 1.20(.047)MAX Mounting height 1 20 0.50(.020) TYP 0.22 -0.04 +.002 .009 -.002 +0.05 0.08(.003) "A" M 0~8 0.100.05(.004.002) (Stand off height) 0.25(.010) 0.45/0.75 (.018/.0295) 0.08(.003) C 1997 FUJITSU LIMITED F80028S-1C-1 Dimensions in mm (inches) 66 MB90F244 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9807 (c) FUJITSU LIMITED Printed in Japan 67 |
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